Mos-transistor for a photo cell

ABSTRACT

The invention relates to a MOS transistor for a photo cell, comprising a semiconductor substrate on which a gate electrode, a drain electrode and a photosensitive source region are configured. An oxide layer is arranged between the gate electrode and the substrate, and in the active region of the MOS transistor this oxide layer is formed as thin oxide film while it is configured as thick oxide film in a passive region.  
     The inventive transistor is distinguished by the provisions that the gate electrode comprises a closed annular section in the active region of the MOS transistor, and that either the drain electrode or the photosensitive source region is arranged within the annular section of the gate electrode so that current will only flow in the active region (FIG.  4 ).

DESCRIPTION

[0001] The invention relates to a MOS transistor for a photo cell, comprising an active region and an isolating passive region joining the active region, wherein a photosensitive source zone, a drain electrode and a gate electrode are formed on the active region.

[0002] It is known from the German Patent 42 09 536 C2 to use such a MOS transistor in a photo cell for a pick-up chip. Such a pick-up chip comprises a plurality of photo cells arranged in two-dimensional arrays, which are each connected to a read-out logic for projection of a high input signal dynamic ratio to a reduced output signal dynamic ratio.

[0003] This photo cell is coupled to a read-out logic which is designed for projection of a high input signal dynamic ratio to a reduced output signal dynamic ratio so that a main electrode of a first photosensitive MOS transistor is connected to the gate of a second MOS transistor, that a control voltage is applied to the gate of the first MOS transistor, which serves to control the compression of the input signal dynamic ratio, that the other main electrode of the second MOS transistor is at a common potential, and that an output signal amplifier is connected to the second main electrode of the second MOS transistor.

[0004] When the drain electrode and the gate of the first transistor are shorted and connected to a fixed potential a precisely logarithmic output characteristic is achieved over a range of more than seven decades, which characteristic allows for a radiometrically unambiguous evaluation of the information in the picture.

[0005] For an improvement of the resolution of an array equipped with such photo cells it is necessary that the photo cell miniaturisation be continued. One method suitable for a further miniaturisation of the transistors of a photo cell is the so-called STI (shallow trench isolation) method wherein the active zones of the transistors are isolated by means of a trench filled with an oxide, with the electrode material for the gate electrode being disposed in strip form across the direction of current flow. The active zone (semiconductor material) is thus framed laterally by two isolating passive zones (oxide), with the gate electrode extending from a passive zone all over the active zone to the other passive zone (cf. Somnath Nag “Shallow trench isolation for sub-0.25 mm IC technologies” in: Solid State Technology, 1997, vol. 40, No. 9, pp. 129-135).

[0006] Even though this transistor, which is configured by means of the STI method, is fundamentally suitable for use as photosensitive element in the photo cell mentioned by way of introduction, such transistors produced with the STI technique present parasitic transistors at the interfacial regions between the active region and the isolating oxide regions. These parasitic transistors make themselves notices at the characteristic in the low signal strength range, the so-called “subthreshold” range. This part of the characteristic should follow an exponential course if the gate and the drain electrode are connected to the same potential. Due to the parasitic transistors, however, another signal is superimposed on the characteristic having an inherent exponential course, which signal is partly essentially stronger than the signal proper and hence interferes with the exponential course. A transistor manufactured with the STI technique, which can be miniaturised, is therefore not suitable for the photo cell mentioned by way of introduction, on account of these parasitic transistors.

[0007] The invention is now based on the problem of providing a MOS transistor for a photo cell, which allows for a further miniaturisation of the photo cell and which is moreover suitable for generating an exponential characteristic of the photo cell. This problem is solved by a MOS transistor having the features defined in claim 1. Expedient improvements of the invention are defined in the dependent claims.

[0008] Due to the inventive configuration of the MOS transistor, which comprises an annular region following the gate electrode and where the drain electrode or the photosensitive source region, respectively, is disposed within the annular gate electrode, produces the effect that the current flows in a radial direction towards the centre or away from the centre of the annular region of the gate electrode. Thus a flow of current along the transition zone between the active and passive regions is not created so that any parasitic marginal effects are precluded.

[0009] The gate electrode comprises an appendix which crosses merely either the active source region or the drain electrode so that it does not take any influence on the characteristic of the inventive MOS transistor. The appendix rather permits the establishment of the electric contact of the gate electrode with an electric conductor above the passive region, as is necessary due to the manufacturing conditions.

[0010] With the inventive configuration of the MOS transistor eliminating any parasitic marginal effects, the STI method can be applied for producing it so that the passive isolating regions can be kept very narrow. The inventive MOS transistor is therefore better to miniaturise than comparable conventional transistors and permits the production of photosensitive arrays having a high resolution.

[0011] In a preferred embodiment the gate electrode and the drain electrode are connected to the same electrical potential so that the MOS transistor presents a logarithmic characteristic extending over several decades.

[0012] The invention will be described in the following by exemplary embodiments, without any restriction of the general inventive idea, with reference to the schematic drawing wherein:

[0013]FIG. 1 is a plan view of an inventive MOS transistor,

[0014]FIG. 2 shows an equivalent circuit diagram for the transistor according to FIG. 1,

[0015]FIG. 3 is a diagram representing the characteristic of the transistor according to FIG. 1 and the characteristic of a conventional transistor produced in accordance with the STI method, and

[0016]FIG. 4 is a simple perspective view of the inventive transistor for illustration of the flow of current.

[0017] The inventive MOS transistor 1 is configured on a semiconductor substrate 2 such as a silicon substrate (FIG. 4). A gate electrode 3 is formed on the semiconductor substrate 2, which, in a manner known per se, consists of an oxide layer 4 applied directly on the substrate 2, and of a polysilicon layer 5 deposited thereon. The oxide layer 4 has a thinner configuration in an active region or channel region 6 of the transistor, than in an adjacent passive region. In a manner known per se the doping in the semiconductor substrate 2 may also change at the junction from the active region 6 to the passive region 7.

[0018] In accordance with the invention the gate electrode 3 presents an annular section 8 which is disposed on the active region 6 of the transistor 1. An appendix 9 of the gate electrode 8 leads from the annular section 8 of the gate electrode 3 up to the passive region 7, which means that the oxide layer 4 between the polysilicon layer 5 and the semiconductor substrate 2 passes over from a thin oxide film 4 a to a thick oxide film 4 b in the transition zone 10 from the active region 6 to the passive region 7 which is disposed below the appendix 9. The plan view shows that the appendix, which is arranged in the passive region 7, is widened to form a square pad area on which an electrical conductor (not illustrated) can be contacted.

[0019] A drain electrode 12 is arranged within the annular sections 8 of the gate electrode 3.

[0020] A photosensitive source region 13, where charge carriers can be generated by irradiation of photons, is arranged outside the annular section 8 of the gate electrode 3. The charge carriers derive to the drain electrode 12 generate a photo current. The photo current is schematically illustrated in FIG. 4, with radial orientation of the flow of current to the drain electrode 12, which means that the photo current radiates from the source region 13, i.e. the zone beyond the ring 8 of the gate electrode 3, to the drain electrode 12 which is arranged in the centre of the annular section 8.

[0021] In the inventive arrangement of the electrodes 3, 12, 13 hence a photo current does not exist which flows along the transition zone 10. As there is no flow of current in the substrate 2 in the transition zone 10 parasitic transistors can actually not be created as is the case in conventional transistors manufactured in accordance with the STI method.

[0022] What is thus essential of the invention is the fact that the flow of current is restricted to the active region 6 and that a flow of current along the transition zone 10 is avoided. This effect is achieved by the annular section 8 of the gate electrode 3, which is arranged at a spacing from the transition zone 10.

[0023] It is also possible within the scope of the invention that the photosensitive source region may be arranged within the annular section 8 and that the drain electrode 12 is arranged outside the annular section 8. For a photo cell, however, the embodiment with the drain electrode 12 inside the annular section 8 a of the gate electrode 3 is preferred, which is illustrated in FIG. 1, as it is possible with these provisions to detect a wide photosensitive source region 13 with a comparatively small electrode surface.

[0024] Within the scope of the invention it is also possible to vary the shape of the annular section 8 and adapt it to the general geometric conditions. For instance, the annular section may present a circular, square, rectangular, oval or similar configuration when seen in a plan view.

[0025] The manufacture of the inventive MOS transistor 1 in accordance with the STI method makes it possible that the thick oxide film 4 b may present a very short or narrow shape, when seen in a plan view, so that the passive region 7 may be kept very narrow. A narrow passive region 7 permits a reduction of the total surface of the transistor 1, compared against convention transistors, which allows for a further miniaturisation. Apart therefrom, a narrow passive region produces the effect that, compared with known transistors, the percentage of the active region 6, particularly the photosensitive source region 13, will be increased, which improves the photosensitivity of an individual transistor. The inventive MOS transistor hence enables the manufacture of a pick-up chip with a higher resolution (more photo cells per unit area), with each photo cell having a higher sensitivity, compared against conventional photo cells, because the percentage of the photosensitive area can be enlarged.

[0026] The transistor illustrated in FIG. 1 comprises a thin metal film 14 which establishes the electrical connection between the gate electrode 3 and the drain electrode 12 and which is isolated from the substrate 2. With this provision the gate electrode 3 is shorted with the drain electrode 12, which furnishes a logarithmic current/voltage conversion (cf. graph 15 in FIG. 3). This graph 15 presents a precisely logarithmic course over a range extending beyond more than 7 decades.

[0027] The equivalent circuit diagram of the transistor 1 with the shorted drain and gate electrodes 12, 3 is illustrated in FIG. 2, with the gate and drain electrodes 3, 12 being connected to ground. For the output voltage V_(OUT) the following relationship applies:

V_(OUT)˜a+V₀log(I_(d)/I₀)

[0028] wherein a, V₀, I₀ are constants and I_(d) represents the drain or photo current, respectively.

[0029] For comparison FIG. 3 illustrates the characteristic curve 16 of a transistor produced in accordance with the STI method and comprising a drain electrode shorted with the gate electrode. As a result of the parasitic transistors explained by way of introduction, its characteristic curve 16 presents a hunch in the section of V_(OUT)<1 V, the sub-threshold section, compared against the characteristic 12 of the inventive transistor 1, which follows a straight course in the logarithmic diagram. This hunch is created by the additional parasitic transistors which generate additional currents which are superimposed with the current of the main transistor.

[0030] The inventive annular configuration of the gate electrode eliminates such parasitic currents in the transistors manufactured in accordance with the STI technique.

[0031] The inventive MOS transistor 1 is preferably employed as photosensitive element for a photo cell of a pick-up chip including an electronic analyser. Such an electronic analyser may comprise an electronic read-out system which is designed for projecting a high input signal dynamic ratio to a reduced output signal dynamic ratio. In such a case the inventive MOS transistor with a main electrode is preferably connected to the gate electrode of a second MOS transistor so that a control voltage is applied to the gate electrode of the photosensitive transistor, which may be used to control a compression of the input signal dynamic ratio, whilst the other main electrode of the photosensitive transistor and the first main electrode of the second transistor are connected to a common potential, and that an output signal amplifier is connected to the second main electrode of the second transistor. This preferred circuit is disclosed in more details in the German Patent DE 42 09 536 C2 which is herewith referenced in terms of its complete contents.

LIST OF REFERENCES

[0032]1 MOS transistor

[0033]2 semiconductor substrate

[0034]3 gate electrode

[0035]4 oxide layer

[0036]4 a thin oxide film

[0037]4 b thick oxide film

[0038]5 polysilicon layer

[0039]6 active region

[0040]7 passive region

[0041]8 annular section

[0042]9 appendix

[0043]10 transition zone

[0044]11 pad area

[0045]12 drain electrode

[0046]13 source region

[0047]14 metal film

[0048]15 characteristic

[0049]16 characteristic 

1. MOS transistor for a photo cell, comprising a semiconductor substrate (2) on which a gate electrode (3), a drain electrode (12) and a photosensitive source region (13) are formed, with an oxide layer (4) being disposed between said gate electrode (3) and said substrate (2) and with said oxide layer (4) being configured as thin oxide film (4 a) in an active region (6) of the MOS transistor (1) and as thick oxide film (4 b) in a passive region (7) of the MOS transistor, characterised in that said gate electrode (3) comprises a closed annular section (8) in said active region (6) of the MOS transistor (1), and that either said drain electrode (12) or said photosensitive source region (13) is arranged within said annular section (8) of said gate electrode (3) so that a flow of current, which is controlled by said gate electrode, will take place only in said active region (6).
 2. MOS transistor according to claim 1, characterised in that said gate electrode (3) comprises an appendix (9) which extends from said annular section (8) up to said passive region (7), with said gate electrode (3) being contacted with an electrical conductor by its zone arranged on said passive region (7).
 3. MOS transistor according to claim 1 or 2, characterised in that said drain electrode (12) is arranged within said annular section (8) of said gate electrode (3) and that said photosensitive source region (13) is formed outside said annular section (8).
 4. MOS transistor according to any of the claims 1 to 3, characterised in that said thick oxide film (4 b) is produced in accordance with the STI method.
 5. MOS transistor according to any of the claims 1 to 4, characterised in that said semiconductor substrate (2) consists of silicon.
 6. MOS transistor according to the claims 1 to 5, characterised in that said gate electrode (3) is formed by a polysilicon layer (5) applied on said oxide layer (4).
 7. MOS transistor according to any of the claims 1 to 7, characterised in that, seen in a plan view, said annular section (8) presents a circular, oval or rectangular shape.
 8. MOS transistor according to any of the claims 1 to 7, characterised in that said gate electrode (3) and said drain electrode (12) are connected to the same electrical potential.
 9. MOS transistor according to claim 8, characterised in that an electrical connection is provided between said gate electrode (3) and said drain electrode (12) in the form of a thin metal film (14) applied thereon which is, however, isolated from said substrate.
 10. Photo cell for a pick-up chip comprising an electronic analyser and a MOS transistor as photosensitive element, characterised in that said MOS transistor is configured in accordance with any of the claims 1 to
 9. 11. Photo cell for a pick-up chip according to claim 10, characterised in that the logic read-out system is designed for projection of a high input signal dynamic ratio to a reduced output signal dynamic ratio, and that the MOS transistor with a main electrode, which constitutes said photosensitive element, is connected to the gate electrode of a second MOS transistor, that a control voltage is applied to the gate electrode of said photosensitive MOS transistor, which can be used to control a compression of the input signal dynamic ratio, that the other main electrode of said photosensitive MOS transistor and the first main electrode of said second MOS transistor are connected to a common potential, and that an output signal amplifier is connected to the second main electrode of said second MOS transistor.
 12. Pick-up chip, characterised by a plurality of photo cells disposed in a two-dimensional array, which are configured in accordance with claim 10 or
 11. 